The invention relates to the field of digital phase locked loops, and, more particularly, to a method and device for reducing the level of parasitic lines from an oscillator controlled by a phase locked loop.
Phase locked loops (PLL) are used, for example, every time there is a need to create a frequency in an electronic apparatus having a specified value that remains stable over time. Information on the design of such circuits is available in a book by Ulrich L. Rohde titled xe2x80x9cDigital PLL Frequency Synthesizersxe2x80x94Theory and Designxe2x80x9d, published by Prentice Hall Inc., Englewood Cliffs, N.J., 07632, under reference No. ISBN 0-13 21439-2. Such a device is used to generate a high frequency signal in a precise and controlled manner, such as from 100 MHz to several GHz, for example.
FIG. 1 shows the traditional structure of a digital phase locked loop. A reference signal Fref, generally coming from an oscillator 1 controlled by a quartz crystal 2, is applied to a phase comparator 3 via a frequency divider 4. The phase comparator 3 is the heart of the PLL, and controls a voltage controlled oscillator VCO 6 via a loop filter 5. The signal coming from the VCO 6 is generally applied via a loop divider 7 to the comparator 3, which sends the signal again around the loop. The signal may be from the VCO 6 or an intermediate signal from the loop divider 7.
By adjusting the division ranking and the reference and loop dividers, the frequency of the output signal can be changed. The output signal frequency is then fed back to control the reference frequency Fref. The spectral frequency and the stability of the output signal are fixed by the characteristics of the loop and by the performance of the reference signal.
With regard to the traditional structure of the PLL illustrated in FIG. 1, particular interest will now be directed to the circuit connected to the output of the phase comparator 3. Ways of creating a phase comparator circuit are given, for example, in the above referenced book by Rohde, particularly on page 11.
The phase frequency comparator or detector (PFD), which may be called a three state comparator, has one state where the phase of the VCO is delayed with respect to the reference phase, one state where the phase of the VCO is in advance of the reference phase, and another state called the equilibrium state where these phases are in phase or within areas of phase advance or phase delay for which the phase loop is not able to react.
The three state phase frequency comparator has the best performance with respect to capture and linearity, and is the phase comparator that is most often used. This PFD is generally connected to a charge pump 16 whose role is to supply a current related to the relative situation of the inputs to the comparator, Fref and FVCO.
FIG. 2 represents in greater detail the phase comparator 3 and a charge pump circuit 16 connected immediately at an output thereof. The phase comparator 3 includes a first 8 and a second 9 input for receiving respectively the reference frequency Fref and a frequency FVCO coming from the VCO. The phase comparator 3 includes two logic outputs 10, 11 respectively called up and down. These outputs 10, 11 control current generators 12, 13 via respective control inputs 14 and 15.
The current generators 12, 13 together form the charge pump 16 of the voltage controlled oscillator 6. The generators 12, 13 supply current that are in principle equal, but in the opposite direction. Because of the manufacturing tolerances, an imbalance generally exists between the absolute values of the currents supplied by the generators 12 and 13.
The operation of this circuit will now be explained with reference to FIGS. 3 to 5, which represent different signals. The signals represented by lines A and B in FIG. 3 represent the form of periodic square signals obtained in a known way from frequencies generated by the reference oscillator 1 and the VCO 6.
In the example shown, for lines A and B the falling edge of the VCO signal is delayed with respect to the rising edge corresponding to the Fref signal, as shown within the ring C. An enlarged view of the temporal relationship between these two edges is shown by lines D and E. The value on the logic outputs 10 and 11 is represented on lines F and G respectively. The charge pump 16 current is shown by line H. This may be a positive current of value +I, a negative current of value xe2x88x92I, or a zero current if neither or both of the two current generators 12 and 13 produce current.
A falling edge for the Fref frequency arriving before the falling edge of the VCO frequency will generate the up output 10 (line F) having logic value 1, for example, commanding generator 12 to supply current. The arrival of the falling edge of the VCO frequency (line E) will generate the output 10 of the comparator 3 having a logic value 0, for example, commanding the generator 12 to switch off. Generator 12 will thus charge the pump for a period of time equal to the phase delay between FVCO and Fref. This charging has the effect of bringing the phase delay back to 0.
Referring now to FIGS. 4 and 5, what occurs when the frequency FVCO is in advance or in phase with respect to the frequency Fref will now be examined. In FIG. 4, the falling edge of the signal FVCO represented by line E arrives before the falling edge of the signal Fref represented by D. Under these conditions, the operation of the comparator 3 is such that the falling edge of signal FVCO will cause a change in the logic value present at output 11 (line G) of the comparator 3. This value is set at 1, for example.
This output will generate the command 15 for the generator 13. A current in the opposite direction to that in the preceding case, as mentioned in connection with FIG. 3, will be passing through the charge pump 16. The subsequent arrival of the falling edge of the Fref signal will cause the logic value at output 11 (down) from the comparator 3 to return to the previous logic value 0, for example, which is line G in FIG. 4. Hence the current flow from generator 13 (line H) is stopped.
In FIG. 5, the signals Fref and FVCO, i.e., lines D and E are in phase. Under these conditions, the logic values on outputs 10 and 11, i.e., lines F and G, do not change. The current I, i.e., line H, is zero. The operation which has just been described in connection with FIGS. 3 to 5 does not discuss reaction times of the phase comparator 3 which will be referred to as Tpfd, and the reaction times of the current generators will be referred to as Tcp. Due to these reaction times there are phase delay and advance areas close to the area referred to as the equilibrium area represented in FIG. 5. This is where the Fref and FVCO phases are in phase, and wherein the comparator 3 and the pump 16 do not have time to react.
In FIG. 5, the situation is shown in which the delay of the falling edge of signal FVCO is slightly delayed or slightly in advance of the falling edge of the Fref signal and is situated, for example, within the hatched area shown in E in FIG. 5. This hatched area in FIG. 5 corresponds to double the minimum time required to start the flow of current from generator 12 or 13.
Within the time interval represented by the hatched area, the charge pump 16 has not yet reacted to the command provide current when it receives the command to stop providing current. Hence, with regard to the control exerted on the frequency FVCO by the phase locked loop, the result illustrated by the curve shown in FIG. 6 is obtained. This curve shows the output power on the y-axis as a function of the frequency on the x-axis. This curve also shows two plateau areas, substantially symmetrical to one another with respect to an axis YYxe2x80x2, corresponding to the value FVCO.
A frequency range marked C, for which the axis YYxe2x80x2 is an axis of symmetry, corresponds to an area where, due to reactions times Tpfd and Tcp, no control is exerted over the output frequency FVCO. The frequency areas marked a and b in FIG. 6 correspond to areas where, because of the phase control loop, the operation of the VCO will be servo-driven in a stable fashion. Areas d and e, positioned in a substantially symmetrical fashion with respect to one another, correspond once again to frequency ranges where regulation is no longer exercised.
In the uncontrolled areas c and d and e, the output power is regulated by the characteristics of the oscillator VCO 6. The operation of the loop which has just been described leads to strong phase noise in the area c around the central frequency VVCO. This forms a major defect in many applications. One known aproach to remedy this defect includes re-injecting, in a systematic way, a current pulse of predetermined duration triggered by the falling edge of Fref. This re-injection takes place on the slowest path triggered by Fref, and the duration is fixed by design to ensure a current pulse regardless of the conditions of use of the phase locked loop.
A diagram showing an example of a circuit used for the re-injection is shown in FIG. 7. Compared with the circuit shown in connection with FIG. 2, the known re-injection circuit intended to avoid the uncontrolled area c comprises a charge re-injection circuit 17 in the form of a generator which generates a pulse of predetermined duration.
An input 18 to this generator 17 receives Fref, and an output 19 carrying the output pulse supplies a first input 23 to an OR gate 20. A second input 22 to this gate receives the output (up) from the comparator 3. An output 21 from the OR gate 20 commands the current generator 12. Hence, the current generator 12 is commanded to pass the pulse supplied by the pulse generator 17 for at least the duration q of the pulse.
The operation of this re-injection circuit will now be explained with reference to FIGS. 8 to 10. These figures use the same annotations as those used in FIGS. 3 to 5. FIG. 8 represents the case where the phase delay of the signal FVCO is greater than the duration q represented by a hatched area on line H of the pulse supplied by the pulse generator 17. In this case, the current generator 12 will be commanded to pass current by the two inputs of the OR gate 20. The flow time of generator 12 due to the pulse from generator 17 is less than the flow time necessary to come back into phase. The operation is identical to that described in connection with FIG. 3. The pulse of duration q changes nothing.
In the case shown in FIG. 9 where the frequency FVCO is phase advanced by a period of time d with respect to Vref, one will have an operation identical to that described in connection with FIG. 4. There will be a triggering of a discharge current from generator 13 for the duration of the phase displacement. However, the arrival of the falling edge Fref will trigger the pulse generator 17. This will cause a charge current for the duration q of the pulse. The phase loop will operate in such a way that the mean sum of the negative current and the positive current recenters the loop to obtain the frequency FVCO.
When in the area of equilibrium as FIG. 10 shows, the current is present in an alternating way in generators 12 and 13 so that there is an oscillation at frequency Fref. The spectrum then has the throughput shown in FIG. 11. There is a power peak at frequency FVCO, and in addition, peaks repeated at frequency intervals separated by the value of the frequency Fref. These peaks are a nuisance since, for example, they interfere with adjacent channels.
The inventor has noted that the parasitic peaks are separated from one another by intervals equal to the value of the frequency Fref, and have an amplitude which increases with the duration of charge. The invention therefore reduces as much as possible the charge duration, and hence, the amplitude of the variation of the charge which is proportional to the duration q of the pulse generated by the generator 17. In this way, the amplitude of the peaks that are parasitic to the frequency Fref are reduced. The duration q of the pulse from the generator 17 according to the prior art and shown in FIG. 7 must be greater than the reaction time TPFD of the phase comparator 3 increased by the reaction time TCP of the current generator 12 or 13.
To obtain this result regardless of the operating conditions, a value greater than this reaction time is determined on several samples under laboratory conditions. Then, to be sure that the duration q remains greater than the reaction time under the most unfavorable conditions, the minimum time determined is multiplied by a factor of between 5 and 10. The most unfavorable conditions include temperature extremes, components at extreme tolerance limits, and variation of power supply voltages, for example. In most cases, the result is that it is possible to reduce the time q, and hence, reduce the intensity of the peaks parasitic to the frequency Fref.
The reaction time of the phase locked loop is, as has already been explained above, the time which passes between the arrival of the charge command and the moment when the charge current generator passes a significant level of current. Therefore, a detector of the current passed by the charge current generator is put into place. The detector changes the logic level when the value of the current generated by the current generator becomes greater than a threshold value, and the changing of this logic value will be used to change the logic level at the output of the pulse generator.
Despite the additional transit times due to the reaction times of the detector and any possible additional circuits, an additional pulse duration time q will be obtained that is quasi-equal to the reaction time of the loop.
The present invention relates to a phase locked loop for a voltage controlled oscillator. The loop comprises a phase comparator receiving at its input a reference frequency and a frequency coming from the oscillator. Logic values are supplied to command a charge pump. A charge re-injection circuit receives one of the inputs from the comparator and supplies a logic value to command the charge pump. The phase locked loop further comprises a detector of a threshold value of a current representative of the current supplied by the charge pump. A logic output from the detector is applied on return to the charge re-injection circuit in a way that limits the duration of the charge re-injection.
The current detector could be coupled either to the current generator effectively included in the charge pump, or to an additional generator that is identical to the current generator included in the pump.
The approach with an additional generator has the disadvantage, due to manufacturing tolerances, of having a triggering threshold which can be slightly offset in time in relation to the triggering threshold of the generator included in the pump. To overcome this disadvantage, the threshold for the current value triggering the change of logic level of the detector could be fixed at a value slightly greater than the value that would be used for the generator in the pump. The advantage of the additional generator is that the presence of the detector and of the additional generator does not interfere with the operation of the charge pump.
In a particularly advantageous embodiment, the input to the charge re-injection circuit is not coupled to the input of the comparator receiving the reference frequency, but to the input of the comparator receiving the frequency from the output of the oscillator. This embodiment has the advantage of further reducing the value of the mean charge current so that the height of the parasitic peaks separated from one another by the value of the frequency Fref is reduced.
The invention also relates to a method in which the duration of the re-injection is limited, not as a function of the predetermined reaction time of the phase locked loop, but as a function of the instantaneous reaction time of the phase locked loop itself.